The present invention relates to an improvement in level shift circuits for level shifting a low voltage signal to a high voltage signal to perform a signal transfer between two different circuits which are operated by different power supply voltages.
Recent increasing demand for low-power electronic devices has caused the power supply voltage of LSI internal circuits to decrease to 3 volts, to 2.5 volts or to less than 2.5 volts. This produces some necessities. For example, if an LSI external circuit is operated by 5 volts in contrast with the fact that the power supply voltage of a corresponding LSI internal circuit is 3 volts or less, this results in the requirement that an amplitude of 5 volts be provided. To this end, it is required to provide a level shift circuit capable of shifting either an amplitude of 3 volts, an amplitude of 2.5 volts or an amplitude of less than 2.5 volts to an amplitude of 5 volts.
Referring first to FIG. 10, there is shown an example of a conventional level shift circuit. Reference numeral 301 designates a signal input terminal. The signal input terminal 301 receives a low voltage (3 volts) signal from an inverter (an external circuit) 20 which is operated by low oltages (e.g., 3 volts). 302 designates an output signal terminal at which a high voltage (5 volts) signal is output to an operating circuit (not shown in the figure) which is operated by higher voltages (e.g., 5 volts).
Referring still to FIG. 10, 401 designates a first power supply terminal which is coupled to a low voltage power supply (e.g., a 3-V power supply). 402 designates a second power supply terminal which is coupled to a high voltage power supply (e.g., a 5-V power supply). 304 designates an N-channel MOS (Nch) transistor having (i) terminals of which one is coupled to the signal input terminal 301 and (ii) a gate which is coupled to the first power supply terminal 401. 303 designates an inverter made up of an Nch transistor 306 and a P-channel MOS (Pch) transistor 307. The inverter 303 receives its operating voltage from the second power supply terminal 402. The inverter 303 has an input coupled to the other of the terminals of the Nch transistor 304. Further, the inverter 303 has an output coupled to the output signal terminal 302. 305 designates a Pch transistor having terminals, namely a drain, a source, and a gate, wherein the drain terminal is coupled to the input of the inverter 303, the source terminal is coupled to the second power supply terminal 402, and the gate terminal is coupled to the output of the inverter 303. 403 designates an intermediate node between the Nch transistor 304 and the inverter 303.
Referring to FIG. 11(a), the operation of the level shift circuit of FIG. 10 will be described below.
Upon application of a signal which changes in voltage level from LOW (0 volt) to HIGH (3 volts) at the signal input terminal 301, the intermediate node 403 is pulled up to a voltage level (3xe2x88x92Vtn) through the Nch transistor 304 in the ON state, where Vtn represents the threshold voltage of the Nch transistor 304. If the switching voltage of the inverter 303, Vo. is set lower than the voltage (3xe2x88x92Vtn), this causes the output signal terminal 302 to decrease from HIGH (5 volts) towards LOW (0 volt) by signal inversion.
Because of a gate potential drop, the Pch transistor 305 goes into the ON state from the OFF state, and the intermediate node 403 is pulled up to HIGH (5 volts). Accordingly, the potential of the output signal terminal 302 is decreased to a lower value, finally arriving at LOW (0 volt). The Nch, transistor 304 comes to have a gate potential equal to or less than its source and drain potentials, as a result of which the Nch transistor 304 changes to the OFF state. Accordingly, there exists no current path extending from the high voltage power supply to the low voltage power supply, which makes it possible to perform a voltage level shifting operation in the steady state with direct currents cut off.
Next, upon application of a signal which changes in voltage level from HIGH (3 volts) to LOW (0 volt) at the signal input terminal 301, the gate potential of the Nch transistor 304 will relatively increase. The Nch transistor 304, therefore, changes to the ON state. The intermediate node 403 is decreased from HIGH (5 volts) towards LOW (0 volt). The Pch transistor 305 is in the ON state and the potential level of the intermediate node 403 is determined by the value of a sum of the ON resistance of the Nch transistor 304 and the ON resistance of the external circuit 20 which drives the signal input terminal 301 with respect to the ON resistance of the Pch transistor 305. That is, as the ON resistance of the Pch transistor 305 relatively increases, the potential level of the intermediate node 403 decreases. Accordingly, if the Pch transistor""s ON resistance is set sufficiently greater than the aforesaid sum, this causes the intermediate node 403 to have a potential level below Vo (the inverter""s 303 switching voltage) and signal conversion causes the output signal terminal 302 to increase from LOW (0 volt) towards HIGH (5 volts).
Because of such an operation, the Pch transistor 305 continues to be boosted in gate potential, and the ON resistance further increases. As a result, the potential of the intermediate node 403 is decreased to a lower value and the voltage of the output signal terminal increases. Finally, the Pch transistor 305 enters the OFF state and the intermediate node 403 arrives at LOW (0 volt) while the output signal terminal arrives at HIGH (5 volts). Also in this case, there exists no current path extending from the high voltage power supply to the low voltage power supply, which makes it possible to perform a voltage level shifting in the steady state with direct currents cut off.
Because of the foregoing operations, a signal of opposite phase to the input signal at the signal input terminal 301 appears at the output signal terminal 302. Such an inverted signal has an amplitude of 5 volts.
However, the above-described conventional level shift circuit has some drawbacks. One drawback is that both the possibility that the operating speed degrades and the possibility that the malfunction occurs increase when the low voltage power supply is decreased in voltage level to a further extent because of demands for lower power LSI circuits.
In the case the, signal input terminal 301 makes a change in voltage level from LOW to HIGH, a voltage level drop occurring in the low voltage power supply results in a speed drop which pulls up the potential of the intermediate node 403, for the drain current is reduced because both the drive performance of the external circuit 20 for driving the signal input terminal 301 and the gate voltage of the Nch transistor 304 in the ON state fall.
The reachable potential of the intermediate node 403 will fall for an amount approximately corresponding to a voltage level drop in the low voltage power supply. If such a reachable potential does not exceed Vo (the switching voltage of the inverter 303), no signal inversion is carried out, which causes the output signal terminal 302 to remain at HIGH. As a result, a malfunction occurs. Such a malfunction may be avoided by reducing the switching voltage. To this end, the gate width of the Nch transistor 306 forming a part of the inverter is required to be set relatively greater than that of the Pch transistor 307. However, the Pch transistor 307 is, of course, required to maintain some drive performance (gate width) and a reduction of the switching potential results in an abrupt increase in LSI pattern area. Therefore, such arrangement cannot be employed.
In addition to the above, if the gate width of the Nch transistor 306 is increased, this results in a gate capacitance load increase. This is a factor of degrading the operating speed.
A drop in the voltage level of the low voltage power supply occurring when the signal input terminal 301 changes in voltage level from HIGH to LOW results in a decrease in operating speed because both the drive performance of the external circuit 20 for driving the signal input terminal 301 and the drive performance of the Nch transistor 304 fall.
Additionally, with respect to the ON resistance of the Pch transistor 305, the foregoing sum increases, which makes it difficult to decrease the level of the intermediate node 403 to a lower value. Accordingly, in this case, it is required to establish a higher switching voltage level in order to ensure that the inverter 303 performs a signal inversion operation. Such a requirement conflicts with the case in which the signal input terminal 301 changes in voltage level from LOW to HIGH. This shows that a voltage level drop in the low voltage power supply results in a reduction in entire operating margin.
Accordingly, an object of the present invention is to provide an improved level shift circuit capable of performing a stable level shifting to shift a low voltage signal to a high voltage signal without the occurrence of degradation in operating speed even when with respect to the high voltage power supply voltage level, the low voltage power supply has a voltage level lower than it has conventionally been assigned.
In order to achieve the object, the present invention provides a level shift circuit which includes a voltage booster for boosting in voltage level an input of an output-stage inverter for converting a voltage level into another above a low power supply voltage level when a signal input terminal changes in voltage level from LOW to HIGH.
Additionally, the level shift circuit of the present invention includes either an Nch transistor for pulling the voltage level of the output-stage inverter input down to a lower value when the voltage level of the signal input terminal changes in voltage level from HIGH to LOW or a voltage booster for driving the Nch transistor.
The present invention provides a level shift circuit which comprises:
(a) a level shift section, including (i) a signal input terminal at which a signal having a voltage level of a first power supply is input and (ii) an inverter which is operated by a second power supply having a voltage level above the first power supply voltage level and which inverts the input signal, for shifting a voltage level of the input signal to a voltage level of the second power supply, and
(b) a first voltage booster which is operated by the input signal and by the first power supply and which generates, in accordance with timing of a transition of the input signal from a LOW to a HIGH level, a signal having a voltage level above the first power supply voltage level and outputs the thus generated signal to the inverter.
The present invention provides a level shift circuit which comprises:
(a) a level shift section, including (i) a signal input terminal at which a signal having a voltage level of a first power supply is input and (ii) a cross latch circuit which is operated by a second power supply having a voltage level above the first power supply voltage level and which receives a signal in phase with the input signal and a negative phase signal with the input signal, for shifting a voltage level of the input signal to a voltage level of the second power supply, and
(b) a first voltage booster which is operated by the input signal and by the first power supply and which generates, in accordance with timing of a transition of the input signal from a LOW to a HIGH level, a signal having a voltage level above the first power supply voltage level and outputs the thus generated signal to the cross latch circuit.
The present invention provides a level shift circuit which comprises:
(a) a level shift section, including (i) a signal input terminal at which a signal having a voltage level of a first power supply is input and (ii) an inverter which is coupled to a second power supply having a voltage level above the first power supply voltage level and which inverts the input signal, for shifting a voltage level shifting of the input signal to a voltage level the second power supply, and
(b) a first voltage booster which is operated by the input signal and by the first power supply and which generates, in accordance with timing of a transition of the input signal from a LOW to a HIGH level, a signal having a voltage level above the first power supply voltage level and outputs the thus generated signal to the inverter,
the level shift section further including a first N-channel MOS transistor having (i) terminals of which one is coupled to a ground power supply and the other is coupled to an input of the inverter and (ii) a gate at which a negative phase signal with the input signal is input.
In the above-described level shift circuit in accordance with the present invention, the first voltage booster further includes a pump circuit for boosting the generated signal to a higher voltage level.
In the above-described level shift circuit in accordance with the present invention, (a) a third N-channel MOS transistor is provided having (i) terminals of which one is coupled to a ground power supply and (ii) a gate which is coupled to the signal input terminal, (b) the gate of the first N-channel MOS transistor in the level shift section is not fed a negative phase signal but is coupled to the other of the terminals of the third N-channel MOS transistor, (c) a second voltage booster is provided having an output which is coupled to the gate of the first N-channel MOS transistor, and (d) the second voltage booster is operated by the input signal and by the first power supply and generates, in accordance with timing of a transition of the input signal from a HIGH to a LOW level, a signal having a voltage level above the first power supply voltage level and outputs the thus generated signal to the gate of the first N-channel MOS transistor.
In the above-described level shift circuit in accordance with the present invention, the second voltage booster further includes a pump circuit for boosting the generated signal to a higher voltage level.
In the above-described level shift circuit in accordance with the present invention, (a) the pump circuit is provided plurally in number and (b) these pump circuits are connected in series so that the generated signal is boosted in voltage level plural times.
The present invention provides the following advantages. In accordance with the present invention, even for the case of a signal which is input at the signal input terminal and which has a low-degree HIGH level (e.g., 2 volts) not as high as one that has conventionally been applied, such a low-degree HIGH level signal, when input, is boosted in voltage level by the first voltage booster, therefore enabling the boosted voltage level to exceed the switching level of the inverter of the level shift section and that of the cross latch circuit. Accordingly, when the voltage level boosted signal is input to the inverter of the level shift section or to the cross latch circuit, the inverter or the cross latch circuit, whichever has been fed the signal, will perform a HIGH-to-LOW inversion operation without fail to secure a desired operation.
Particularly, in the present invention, at the time when a signal that is applied at the signal input terminal makes a transition to HIGH, a voltage level boosted by the first voltage booster is further increased by the pump circuit, which makes it possible for an input signal to the inverter of the level shift section to assume a voltage level above the switching level of the inverter even when the signal applied at the signal input terminal has a low-degree HIGH level.
In the present invention, the provision of the plural pump circuits can ensure that the voltage level of a signal that is input to the inverter of the level shift section is increased above the switching level of the inverter, therefore providing a greater operation margin to the level shift circuit.
In the present invention, when a signal at LOW is input from the signal input terminal, the first Nch transistor enters the ON state upon receipt of a negative phase signal with that LOW input signal, thereby coupling the input of the inverter to a ground power supply. Accordingly, the potential of the inverter decreases in LOW direction. Here, the pulling down of the inverter input to LOW is performed without involving any external circuit. In other words, such a pulling down operation is unaffected by the ON resistance of an external circuit for driving the signal input terminal, and the voltage level of the inverter input can be decreased to a lower value in comparison with conventional level shift circuits. Accordingly, even when the voltage level of the first power supply is lower than conventionally-used ones, it can be ensured that the inverter performs a LOW-to-HIGH signal inversion operation.
In the present invention, when a signal at LOW is input at the signal input terminal, the third Nch transistor enters the OFF state and the gate potential of the first Nch transistor is increased above at least the first power supply voltage level by the second voltage booster. Since the ON resistance of the first Nch transistor diminishes, the input of the inverter in the level shift section is coupled, through such a diminished ON resistance, to a ground power supply. As a result, the potential of the inverter input is decreased to a further extent. This can further ensure that the inverter performs a LOW-to-HIGH signal inversion operation at a high speed.
In the present invention, a voltage boosted in the second voltage booster is boosted to a higher value by the pump circuit, which makes it possible to decrease the ON resistance of the first Nch transistor to a further extent. This can further ensure that the inverter performs a LOW-to-HIGH signal inversion operation at a high speed.
In the present invention, the second voltage booster is provided with a plurality of pump circuits, which can ensure that the inverter performs a signal inversion operation at a high speed.